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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance
PHP50N06LT, PHB50N06LT, PHD50N06LT
SYMBOL
d
QUICK REFERENCE DATA VDSS = 55 V ID = 50 A
g s
RDS(ON) 24 m (VGS = 5 V) RDS(ON) 22 m (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP50N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB50N06LT is supplied in the SOT404 surface mounting package. The PHD50N06LT is supplied in the SOT428 surface mounting package.
PINNING
PIN 1 2 3 tab DESCRIPTION
SOT78 (TO220AB)
tab
SOT404
tab
SOT428
tab
gate drain1 source
2
2
drain
1 23
1
3
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 13 50 35 200 125 175 UNIT V V V A A A W C
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages. September 1998 1 Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient
PHP50N06LT, PHB50N06LT, PHD50N06LT
CONDITIONS
TYP. -
MAX. 1.2 -
UNIT K/W K/W K/W
SOT78 package, in free air SOT404 and SOT428 package, pcb mounted, minimum footprint
60 50
ESD LIMITING VALUE
SYMBOL PARAMETER VC Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. MAX. 2 UNIT kV
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS V(BR)GSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; IG = 1 mA; VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 5 V; ID = 12.5 A VGS = 10 V; ID = 12.5 A Tj = 175C Forward transconductance VDS = 25 V; ID = 25 A Gate source leakage current VGS = 5 V; VDS = 0 V Tj = 175C Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance VDS = 55 V; VGS = 0 V; Tj = 175C ID = 50 A; VDD = 44 V; VGS = 5 V Tj = -55C MIN. 55 50 10 1.0 0.5 15 TYP. MAX. UNIT 1.5 19 17 40 0.02 0.05 27 4 14 30 80 95 40 3.5 4.5 7.5 1500 300 150 2.0 2.3 24 22 50 1 20 10 500 45 130 135 55 2000 360 200 V V V V V V m m m S A A A A nC nC nC ns ns ns ns nH nH nH pF pF pF
VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
September 1998
2
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V TYP. MAX. UNIT 0.95 1.0 40 0.07 50 200 1.2 A A V V ns C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER WDSS CONDITIONS MIN. MAX. 80 UNIT mJ Drain-source non-repetitive ID = 40 A; VDD 25 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 ; Tmb = 25 C energy
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
120 110 100 90 80 70 60 50 40 30 20 10 0
ID%
Normalised Current Derating
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
20
40
60
80 100 Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
September 1998
3
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
1000
ID / A
7524-55
40
RDS(ON)/mOhm
35
RDS(ON) = VDS / ID 100
VGS/V =
4
4.2
tp = 10 us 100 us
30
4.4 4.6 4.8 5
25
10
DC
1 ms 10 ms 100 ms
20
1
1
10 VDS / V
100
1000
15
10
15
20
25
30
35
40 45 ID/A
50
55
60
65
70
75
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth (K/W)
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
100 ID/A 80
10
1
0.5 0.2 0.1 0.05 0.02 P D tp D= tp T t
60
0.1
40
0.01
0 T
20 Tj/C = 175 0 25
0.001 10us 1ms pulse width, tp (s) 0.1s 10s
0
1
2
3 VGS/V
4
5
6
7
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain current, ID (A) 10 8 6
Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Transconductance, gfs (S) 40
100
VGS = 5.0 V
4.8 4.6 4.4 4.2
35 30 25 20 15 10 5
80
60
4.0 3.8 3.6 3.4 3.2 2.6 3.0 2.8 10
40
20
0
0
2
4 6 8 Drain-source voltage, VDS (V)
0
20
40 60 Drain current, ID (A)
80
100
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
September 1998
4
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
2.5
a
BUK959-60
Rds(on) normlised to 25degC
3
2.5
2
Thousands pF
2
1.5
1.5 Ciss 1
1
0.5
0.5 -100
-50
0
50 Tmb / degC
100
150
200
0 0.01
0.1
1
VDS/V
10
Coss Crss 100
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V
VGS(TO) / V max. 2 typ. 1.5 BUK959-60
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6 VGS/V 5 VDS = 14V 4 VDS = 44V 3
2.5
min. 1
2
0.5
1
0 -100
-50
0
50 Tj / C
100
150
200
0
0
5
10
15 QG/nC
20
25
30
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS
100 IF/A
1E-01
1E-02 2% typ 98%
80
1E-03
60
1E-04
40 Tj/C = 20 175 25
1E-05
1E-05
0
0
0.5
1
1.5
2
2.5
3
0
0.5
VSDS/V
1
1.5
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
September 1998
5
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
PHP50N06LT, PHB50N06LT, PHD50N06LT
120 110 100 90 80 70 60 50 40 30 20 10 0
WDSS%
+
L VDS VGS 0 RGS T.U.T. R 01 shunt
VDD
-ID/100
20
40
60
80
100 120 Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 40 A
Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
September 1998
6
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
PHP50N06LT, PHB50N06LT, PHD50N06LT
4,5 max 10,3 max
1,3
3,7 2,8
5,9 min
15,8 max
3,0 max not tinned
3,0
13,5 min
1,3 max 1 2 3 (2x)
2,54 2,54
0,9 max (3x)
0,6 2,4
Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8".
September 1998
7
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 1.4 g
10.3 max
PHP50N06LT, PHB50N06LT, PHD50N06LT
4.5 max 1.4 max
11 max 15.4
2.5 0.85 max (x2) 2.54 (x2)
0.5
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5 2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
September 1998
8
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
PHP50N06LT, PHB50N06LT, PHD50N06LT
Dimensions in mm : Net Mass: 1.4 g
seating plane 6.73 max 1.1 2.38 max 0.93 max 5.4
tab
4 min 6.22 max 10.4 max 4.6
2 1 3
0.5 min 0.3 0.5
0.5
0.8 max (x2) 2.285 (x2)
Fig.20. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15 2.5
1.5
4.57
Fig.21. SOT428 : soldering pattern for surface mounting.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8".
September 1998
9
Rev 1.400
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHP50N06LT, PHB50N06LT, PHD50N06LT
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
September 1998
10
Rev 1.400

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